Integrated circuits (e.g., miniaturized electronic circuits built into a monolithic semiconductor substrate, such as a silicon chip) are essential for the functionality of many processing systems. A design layout of an integrated circuit may be performed in an automated or semi-automated process using various design software products. Automated systems for producing layouts for an integrated circuit chip may account for numerous factors that provide for mapping, sizing, and placement of components. A design objective generally includes determining an optimal arrangement of components in a plane or a three-dimensional space and an efficient interconnection scheme between the components to provide the desired functionality. Among the components to be arranged in the chip are a large number (e.g., thousands, millions or even billions) of small cells or transistors. Each cell may represent a one or more logic elements, such as a gate, flip-flop, latch, etc., which may perform a specific function. Each cell may include multiple pins or terminals, each of which is connected to pins of other cells by a respective electrical interconnection wire network (or net). A purpose of the optimization process used in the physical design stage of a cell is to determine a cell placement such that all of the required interconnections can be made, but total wire length and interconnection congestion are minimized.
Some processing systems may generate clock signals throughout integrated circuits that include a significant amount of skew relative to the input clock. That is, different components within the integrated circuit may not receive signals from a clock source at the same time. This “clock skew” may be due to a number of causes, including delay induced by on-chip gates and delay induced by on-chip or printed circuit board (PCB) wires.
Clock skew can be accounted for by assuming a worst case delay and synchronizing the clock circuitry accordingly. Thus, during a clock signal process in which less delay than the worst case exists, an unnecessary delay is introduced into the process beyond what is necessary to send/receive the clock signal. This unnecessary delay, when multiplied by numerous data operations, hinders the maximum capability of a data processing system and, thus, limits the quantity of data processed over any given period of time.